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Multifunctional data processor

Find the difference between two numbers

  Use generate...for Statements simplify code

  Use sub modules to compare the size of three input numbers

  Use functions to realize data size conversion

Multifunctional data processor

  This question mainly focuses on Signed number Programming for , There are two points to note about signed numbers ：

（1） At the time of definition , Signed numbers use signed[ : ], for example output reg signed [8:0]c

（2） The highest bit of a signed number is the sign bit , by + perhaps -

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
    input signed[7:0]a,// Signed number 
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);
    
    [email protected](posedge clk or negedge rst_n)begin
        if(~rst_n)begin
            c<=9'b0;
        end
        else begin
            case(select)
                2'd0:c<={a[7],a};// The highest bit is the sign bit 
                2'd1:c<={b[7],b};
                2'd2:c<={a[7],a}+{b[7],b};
                2'd3:c<={a[7],a}-{b[7],b};
                default:  c<=9'b0;
            endcase
        end
    end
      
endmodule

Find the difference between two numbers

  This question is in Chinese if-else Statement can be solved , The code is as follows ：

module data_minus(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,

	output  reg [8:0]c
);
    
    [email protected](posedge clk or negedge rst_n)begin
        if(~rst_n)begin
            c<=9'b0;
        end
        else begin
            if(a>b)begin
                c<=a-b;
            end
            else if(a<b)begin
                c<=b-a;
            end
        end
    end
    
endmodule

  Use generate...for Statements simplify code

  This question mainly examines Verilog in genrate—for Use of statements , and c Languages are similar but different , The process is as follows ：

genvar Variable ;

generate for（ Initial value of variable ; Variable jump ; Variable +1）

        begin：gen_ Variable

                sentence ;

        end

endgenerate·

Be careful ：

Use generate —for Statements must be preceded by genvar Statement declaration variables

generate —for After the sentence begin： You need to add a variable （ Name doesn't matter ）

generate —for  It also needs to be endgenerate by way of conclusion

The code is as follows ：

module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);

    genvar i;
    
    generate for(i=0;i<8;i=i+1)
        begin:gen_i
            assign data_out[i]=data_in[7-i];
        end
    endgenerate
        
  
endmodule

Just to summarize by the way for Use of statements ：

integer Variable ;

for（ Initial value of variable ; Variable jump ; Variable +1）

        begin

                sentence ;

        end

  Use sub modules to compare the size of three input numbers

  This question mainly examines our understanding of “ Exemplification ” Use

According to the title , We need to write a sub module by ourselves first , Realization 2 The function of minimizing the number comparison

Then instantiate 3 Secondary sub module , Input the main module 3 Number abc,a and b Smaller value than output temp1,a and c Smaller value than output temp2, And then temp1 and temp2 Compare , The minimum value is the output

This topic tells us , A sub module can be instantiated many times , Just modify the instantiation name

In the instantiation sub module （ ） The input and output in is the variable of the main module , Can change the name

The code is as follows ：

// The main module compares two sub modules , Output 3 The smallest of the two values 
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
    wire [7:0] temp1;
    wire [7:0] temp2;
     
    junior_mod u1(
        .clk(clk),
        .rst_n(rst_n),
        .a(a),
        .b(b),
        .c(temp1)//a And b The minimum value of comparison is temp1
);
    junior_mod u2(
        .clk(clk),
        .rst_n(rst_n),
        .a(a),
        .b(c),
        .c(temp2)//a And c The minimum value of comparison is remp2
);
        junior_mod u3(
            .clk(clk),
            .rst_n(rst_n),
            .a(temp1),
            .b(temp2),
            .c(d)//temp1 And temp2 The minimum value of comparison is d
);
    
endmodule


// Sub module implementation 2 Compared with 
module junior_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
    output [7:0]c
);

    reg [7:0]c_reg;
    
    [email protected](posedge clk or negedge rst_n )begin
        if(~rst_n)begin
            c_reg<=8'd0;
        end
        else begin
            if(a>b)begin
                c_reg<=b;
            end
            else if(b>a)begin
                c_reg<=a;
            end
        end
    end
    
    assign c=c_reg;
endmodule

  Use functions to realize data size conversion

  This question examines our structural design , We need to build our own functions and tasks ,function and task Is used as follows ：

Mission （task）

（1） Usually used for debugging , Or describe the behavior of the hardware

（2） It can include timing control (# Delay ,, wait)

（3） There can be input, output,  and linout Parameters

（4） You can call other tasks or functions

function（ Mission ）

（1） Usually used to calculate , Or describe combinatorial logic
（2） Cannot include any delay ; The function simulation time is 0

（3） Contains only Input Parameter and return a result by the function name

（4） You can call other functions , But you can't call the task

This problem uses function The code is as follows ：

module function_mod(
    input clk,
    input rst_n,
	input [3:0]a,
	input [3:0]b,
	
	output [3:0]c,
	output [3:0]d
);
function [3:0] begin_end;// Define the function name 
    input [3:0] data_in; // Define input variables 
    
        begin
            begin_end[0]=data_in[3];// Size bit conversion 
            begin_end[1]=data_in[2];
            begin_end[2]=data_in[1];
            begin_end[3]=data_in[0];
        end

endfunction
    
    assign c=begin_end(a);// Call function 
    assign d=begin_end(b);

endmodule