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FPGA majority voter (including code)

2022-07-20 09:56:00 【Juanshi】

Majority voter refers to a decision in which most people agree, that is “1”, The event is “1”, Similar to the previous raise your hand A vote , But now we use electronic means to realize , It is mainly used to express whether the participants are in favor or right , You can quickly calculate the voting results .

If there is 3 Inputs abc, Output is f, The truth table is as follows ：

Use Karnaugh map to simplify （ The explanation of Karnaugh map can be referred to Master Karnaugh map simplification in one minute _ Juanshi's blog -CSDN Blog ）

In the end, we got the result that f=ab+bc+ac

Start writing code ：

module most(
input a,
input b,
input c,
output f
    );
    
assign    f=a&b|a&c|b&c;
endmodule

Test code ：

In limine a=1,b=1,c=0

The back is called a=0,b=1,c=0

module TB_most(

    );

reg a;
reg b;
reg c;
wire f;

most inst_most(
.a(a),
.b(b),
.c(c),
.f(f)
    );
    
    initial begin
    	
    	a=1;
    	b=1;
    	c=0;
    	
    	#20;
    	
    	a=0;
    	b=1;
    	c=0;
    	
    end

endmodule