当前位置:网站首页>Vivado2018.2 version with PS side configuration (BD) when calling Modelsim simulation: (vlog-13006) could not find the package (sc_util_v1_0_3_pkg)
Vivado2018.2 version with PS side configuration (BD) when calling Modelsim simulation: (vlog-13006) could not find the package (sc_util_v1_0_3_pkg)
2022-07-20 09:40:00 【wkonghua】
Use vivado2018.2 Version call modelsim Simulation , The engineering simulation is system level simulation ,PL The side contains all the logic codes of the whole system engineering and pairs PS On the side system To configure (bd). After configuring the simulation environment , adopt vivado call modelsim when , The following error was reported :
# ** Error: ../../../../ZC702.srcs/sources_1/bd/system/ipshared/03a9/hdl/axi_protocol_checker_v2_0_vl_rfs.sv(5554): (vlog-13006) Could not find the package (sc_util_v1_0_3_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# -- Skipping module axi_protocol_checker_v2_0_3_top
# End time: 09:53:31 on Jul 28,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 1
# child process exited abnormally
# Error in macro ./BASEBAND_tb_compile.do line 103
…………
# ** Error: ../../../../ZC702.srcs/sources_1/bd/system/ipshared/03a9/hdl/axi_protocol_checker_v2_0_vl_rfs.sv(5554): (vlog-13006) Could not find the package (sc_util_v1_0_3_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# -- Skipping module axi_protocol_checker_v2_0_3_top
# End time: 09:53:31 on Jul 28,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 1
The error message is displayed in axi_protocol_checker_v2_0_vl_rfs.sv Not found in sc_util_v1_0_3_pkg This package, This problem may be related to vivado The version is about (vivado2018.2 There may be bug), It has been solved after upgrading the version . By upgrading the whole project to 2018.3 After version , No error reported above , You can call modelsim Simulation .
Reference resources :https://forums.xilinx.com/t5/AXI-Infrastructure-Archive/sc-util-v1-0-3-pkg-is-not-declared/td-p/962368
notes : In the use of vivado call modelsim when , You can check it at any time Tcl Console Information in the window , Make targeted modifications according to the prompted information .
边栏推荐
- 论文解读《Beyond Self-attention: External Attention using Two Linear Layers for Visual Tasks》
- [cvpr2020] articles, codes and data links
- How to use pynative mode for migration learning?
- mysql45讲阅读笔记深入浅出索引下(五)
- Thermogram display of pathological tissue section (floating on the surface of tissue section)
- FPGA网口实现与详解(1)
- (数电)各种触发器汇总——FPGA八股文(1)
- How does mindspore view the model parameter quantity?
- Qingdao Weifang becomes a rich man
- 典型的HMI应用实现方案,帮你更好的进行主控选型
猜你喜欢
vivado工程版本升级时相关IP版本IP Status显示Using cached IP results
【mindspore】【import erro】 undefined symbol _ Z14DlogErrorInneriPK
This paper interprets "PSCL hdeep: image-based protein localization using subcellular prediction integrated in human tissue"
基于飞凌NXP i.MX6ULL的无线网络测试
FPGA网口实现与详解(3)
[mindspore] [Lite end-to-side training reasoning] mindspore lit runs the lenet training example code according to the instructions and reports an error
论文解读《DNA Binding Site Prediction Using a Deep Learning Method》
(数电)各种触发器汇总——FPGA八股文(1)
Instructions for torch use
[mindspore] [installation] there is no available ascend 910 AI processor software package
随机推荐
Qualcomm snpe
【mindspore】【import erro】 undefined symbol _ Z14DlogErrorInneriPK
EIM总线如何测试可用性及稳定性
SPIN流程
How to understand the freezing network parameters in the mindscore official website tutorial? Can you explain it?
Redis detailed explanation (2) basic introduction (1) installation and pressure measurement
瑞芯微RK3568开发板深度评测
Xilinx 7系列原语使用(时钟相关)——(一)
基于飞凌NXP i.MX6ULL的无线网络测试
vivado2018.2报错及解决方法记录
论文解读《DNA Binding Site Prediction Using a Deep Learning Method》
3d HMR相关
SMPL模型
How does mindspore view the model parameter quantity?
FPGA网口实现与详解(2)
Difference between up sampling and up convolution
Opencv (1) image reading, display, save, color conversion
xilinx中的复位
FPGA刷题P3: 4位数值比较器电路、4bit超前进位加法器电路、优先编码器电路、 优先编码器
FPGA八股文(2)——笔试的FPGA问题汇总(持续更新)