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Trigger Basics (medium)

2022-07-22 16:03:00 【Li Yuchen】

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Welcome to learn digital circuit ——JK trigger .
Here we will explain JK Triggers and integration JK trigger 74LS112, I hope that through our study, you will better understand the mystery of digital circuits .

Catalog

One 、JK trigger

1.JK Composition and logic function of trigger

（1） Circuit structure and graphical symbols

（2） logic function

2. Integrated edge JK trigger

（1） Edge trigger mode

（2） Integrate JK trigger

One 、JK trigger

1.JK Composition and logic function of trigger

（1） Circuit structure and graphical symbols

JK The trigger is synchronizing RS Based on the trigger, two feedback lines are introduced .

As shown in the figure ：

So when CP=1、R=S=1 when , send $\overline{S}$ =Q、 $\overline{R}$ = $\overline{Q}$ （ namely $\overline{S}$ 、 $\overline{R}$ It's impossible to be 0）, Can fundamentally solve when R=S=1 when , The problem of uncertain trigger output . take S、R The input end is rewritten as J、K Input end , That is to say JK trigger .

Graphic symbols ,C1、1J、1K Is the association mark , Express 1J、1K suffer C1 The control of .

（2） logic function

JK Triggers can not only avoid uncertain States , And the logic function of trigger is added , See table ：

It can be seen from the above that ：

stay CP=0 period ： NAND gate G3、G4 By CP The low level of the terminal is off , Disable the input signal , $\overline{S}$ = $\overline{R}$ =1, basic RS The trigger remains in its original state .

stay CP=1 period ：

① Keep function

When J=K=0 when , NAND gate G3、G4 Output $\overline{S}$ =1, $\overline{R}$ =1, The trigger remains in its original state , namely $Q^{n+1}$ = $Q^{n}$

② Set up 0 function

When J=0、K=1 when , NAND gate G3 Output $\overline{S}$ =1、G4 Output $\overline{R}$ = $\overline{Q}$ . If the original state of the trigger is 0, be $\overline{R}$ =1, The trigger output remains in its original state , That is, the output is 0; If the original state of the trigger is 1, be $\overline{R}$ =0, The trigger output is set to 0.

③ Set up 1 function

When J=1、K=0 when , NAND gate G3 Output $\overline{S}$ =Q、G4 Output $\overline{R}$ =1. If the original state of the trigger is 0, be $\overline{S}$ =0, The trigger output is set to 1; If the original state of the trigger is 1, be $\overline{S}$ =1, The trigger output remains in its original state , Output is 1.

④ Flip function （ Also known as counting function ）

When J=1、K=1 when , NAND gate G3 Output $\overline{S}$ =Q、G4 Output $\overline{R}$ = $\overline{Q}$ . If the original state of the trigger is 0, be $\overline{S}$ =0, $\overline{R}$ =1, The trigger output is set to 1; If the original state of the trigger is 1, be $\overline{S}$ =1, $\overline{R}$ =0, The trigger output is set to 0. That is, the output of the trigger is always opposite to the original state , namely $Q^{n+1}$ = $\overline{Q^{n}}$ .

2. Integrated edge JK trigger

（1） Edge trigger mode

Edge trigger uses the transmission delay time between NAND gates to realize edge control , Make the trigger in CP Rising edge of pulse （ Or the falling edge ） The moment of , Generate a new output state of the trigger according to the state of the input signal ; And in the CP=1（ or CP=0） Period , The input signal has no effect on the state of the trigger . The edge trigger mode ensures that the trigger only acts once during the action of a clock pulse , Effectively overcome the trigger “ Somersault ” The phenomenon .

CP Pulse rising trigger is called positive edge trigger ,CP Pulse falling edge trigger is called negative edge trigger .

edge JK The working waveform and graphic symbols of the trigger are shown in the figure ：

The falling edge trigger in graphic symbols is used in addition to “＞” Outside the symbol , still CP The pin is marked with a small circle .

（2） Integrate JK trigger

① Pin arrangement and graphical symbols

74LS112 The real object of the chip 、 The pin arrangement and graphic symbols are shown in the figure ：

It contains two falling edges triggered JK trigger , $\overline{R_{D}}$ 、 $\overline{S_{D}}$ Is not affected by CP Synchronous pulse control , $\overline{R_{D}}$ It is called direct setting 0 End （ Also known as direct reset end ）、 $\overline{S_{D}}$ It is called direct setting 1 End （ Also known as direct set end ）, $\overline{R_{D}}$ 、 $\overline{S_{D}}$ The small circle at the end indicates Low level active .