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Vivado error code [usf-xsim-62] [xsim 43-4316] solution
2022-07-20 09:03:00 【On the way, starting】
Record this little problem briefly
Catalog
explain
VIVADO IDE :2018.3
operating system :WIN 10
FPGA Chip family :Virtex-7 (xc7vx690tffg1761-2)
Problem description
Let's call this a bizarre case , Last night I was able to perform functional simulation normally , Come here early this morning , Running simulation always reports this error :
[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'E:/MY_PROJECT/RADAR/PCIE_12_CHAN/PCIE_12CHAN_64RCV/PCIE_12CHAN_64RCV.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
Then check the corresponding xvhdl.log file , Find out :
ERROR: [XSIM 43-4316] Can not find file: /sim_1/ip/FIFO_DUALCLOCK/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
Problem solving
In fact, this module is no longer included in my design document , And I have even removed the IP nucleus ( Because it was transplanted by previous projects , This is no longer needed IP It's nuclear ), Still will report this mistake , I have to , Do the following :
1、 According to the wrong path , Copy the documents corresponding to the original project to the current project , And the folder name is consistent with the name required in the error path .
2、 Closure of works
3、 Reopen the project
BUT ! The same error pops up . Or the same mistake , I wonder . Open again xvhdl.log file when , I found that the file has not been modified , And the modification time is not the current time . So I decided to try :
1、 Future generations xvhdl.log file Information in , Save the file after deletion ;
2、 Re execution Functional simulation , It's found to work properly .
What's the cause of the ?
At present, I don't know the root cause of this error , But one thing is certain If you don't know xvhdl.log file Information in , Re execute simulation , Old problems still exist , It really needs to be deleted xvhdl.log file Information in . The other is to pay attention xvhdl.log file Is there any change in the modification time of , If it hasn't changed , That's a high probability to delete xvhdl.log file The error information in the can be solved by saving .
Then if you delete xvhdl.log file And save , Then run the functional simulation again , Then you need to put xvhdl.log file Reported Solve the error and try the above method .
The above is the simulation error [USF-XSim-62] [XSIM 43-4316] The solution , For reference ~
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