• 端接方案对接收端信号质量影响
• 输出驱动强度对接收端信号质量影响
• 负载类型对信号完整性影响
  核心目标：理解端接类型、输出驱动强度和负载类型之间的权衡。

影响接收端信号质量的关键因素如下：
 - Leveling and dynamic ODT
 - Proper use of termination
 - Output driver drive strength setting
 - Loading at the receiver
 - Layout guidelines

Leveling and Dynamic ODT

DDR3 and DDR4 SDRAM DIMMs, as specified by JEDEC, always use a fly-by topology for the 
address, command, and clock signals.

Altera recommends that for full DDR3 or DDR4 SDRAM compatibility when using discrete
DDR3 or DDR4 SDRAM components, you should mimic the JEDEC DDR3 or DDR4 fly-by topology
on your custom printed circuit boards (PCB).

Read and Write Leveling

A major difference between DDR2 and DDR3/DDR4 SDRAM is the use of leveling。

为了改善信号完整性和支持更高频率操作，JEDEC协会定义了时钟，命令和地址总线使用的fly-by端接方案。
read and write leveling 在DDR2和DDR3存在差异，但是DDR4的Leveling技术与DDR3相似

fly-by拓扑通过刻意降低了同步开关噪声(SSN)