Seeing the autumn move , I did some written examination questions of the company , I found that I basically tested various triggers of digital electricity , I forgot everything and confused each other , Today, let's summarize these triggers ！

ps： I found that there are many eight part essays on software development , There are few eight part essays on hardware development , I can only sum it up by myself ,FPGA The eight part essay will be continuously updated , Until I got a job ！

Catalog

Input and output of trigger

Classification of triggers

basic RS trigger

Synchronous trigger —RS trigger

Sync D trigger

Sync JK trigger

Sync T trigger

Input and output of trigger

trigger ： A method with Memory function , Be able to store 0 and 1 Such a circuit of digital information , It is the basic logic device that constitutes the sequential logic circuit

The output state of the trigger ：0 perhaps 1

Trigger output receives Effective excitation signal When ： The state can be reversed 0→1、1→0

If the input excitation signal is not a valid signal ： The output state of the trigger remains unchanged （ Memory function ）

Classification of triggers

Divide according to logical functions ：

RS trigger ： Set up 0 Set up 1 trigger

JK trigger ： Set up 0 Set up 1 And flip trigger

D trigger ： Follow trigger

T trigger ： Flip trigger

According to the internal structure ：（ The structure is becoming more and more complex , The anti-interference ability is improved ）

Basic trigger

Synchronous trigger （ Trigger with clock control ）

Master slave trigger

Edge trigger

basic RS trigger

 RS Triggers have two structures ：

The difference is that input S and D Is it active at high level or active at low level

 S（set） Set up 1 ,R（reset） Set up 0, Output Q by 1 and 0, The truth table corresponding to the above figure is as follows ：

  Substate Q And the present state Q,S,R It's all about

When S and R Values are different ： The excitation signal is valid , Output setting 1 Or set 0

When S and R No input ： Keep the current Q value

When S and R Are effective ： prohibit

  Synchronous trigger —RS trigger

When clk=0, Input excitation is blocked , The output state remains unchanged

When clk=1, The circuit is working , complete RS Trigger function

Sync D trigger

When clk=0, Input excitation is blocked , The output state remains unchanged

When clk=1, The circuit is working , complete D Trigger function

Substate Q and D For the same value （ Follower ）

Sync JK trigger

When clk=0, Input excitation is blocked , The output state remains unchanged

When clk=1, The circuit is working , complete JK Trigger function

J and K There is no incentive ： Keep function

J and K Different ： According to the effective incentive setting 1 or 0

J and K There are incentives ： Secondary meeting “ Flip ” The number opposite to the present state

Sync T trigger

When clk=0, Input excitation is blocked , The output state remains unchanged

When clk=1, The circuit is working , complete T Trigger function

T Incentives are ineffective ： Keep current

T Incentives work ： The secondary state is the result of the inversion of the present state