The design requirements

（1） With display 24 Second timing function ;
（2） The system sets the external operation switch , Direct control of the timer start-up （ Reset to 24） And pause / continue function ;
（3） Timer is 24 Second decrement timing , The time interval is 1 second ;
（4） The timer decrements to zero , The digital display cannot turn off the light , At the same time, the photoelectric alarm signal is sent .

24s count down

Code implementation

Design module

module varmodcnt(CP,CLR,EN,PE,D,Q,carry_out);
parameter n=4,MOD=10;
input CP,CLR,EN,PE;
input [n-1:0] D;
output reg[n-1:0] Q;
output carry_out;
/* Input ：CP Clock signal ,CLR Clear signal ,EN Can make ,PE Prefabricated signal ,D Enter for preset   Output ：Q For export 4 Bit binary number ,carry_out It is a borrow signal */
// Sensitive signals ：CP Rising edge ,CLR Falling edge ,PE Rising edge 
[email protected](posedge CP,negedge CLR)
begin
	if(!CLR)    Q<='d0;   // Zero clearing 
	else if(!EN)    Q<=Q;  // keep , Equivalent to a pause 
	else begin
	    if(Q==4'b0000)    Q<=MOD-1;   // Decline 
	    else	    Q<=Q-1;
	end
end
[email protected](posedge PE)
begin
	Q<=D;            // Set number 
end
assign carry_out=(Q==4'b0000);  // Borrow signal 
endmodule

module _24s(CP,EN,PE,Q1,Q0);
input CP,EN,PE;
output [3:0] Q1,Q0;
/*  Input ：CP For the clock signal ,EN To enable the signal ,PE It is a preset signal   Output ：Q1 Is the number of ten bit outputs ,Q0 Output the number of bits  */
wire carry_out;
wire carry_out1;
wire CP1;
assign CP1=~carry_out;    // The single digits are reduced to 0 when , Ten digit decrement 
wire EN1;
assign EN1=EN&~(carry_out&carry_out1); // When reduced to 0 when , It's not decreasing 
varmodcnt U1(CP1,1'b1,EN1,PE,4'b0010,Q1,carry_out1);   // Component instantiation 
varmodcnt U0(CP,1'b1,EN1,PE,4'b0100,Q0,carry_out);   // Component instantiation 
endmodule

Test module

`timescale 100ms/10ms
module tb_24s();
reg CP;
reg EN;
reg PE;
wire [3:0] Q1;
wire [3:0] Q0;

_24s U(CP,EN,PE,Q1,Q0);  // Component instantiation 

initial 
	$monitor($time,"\tQ1=%b,Q0=%b\n",Q1,Q0);
// The clock 
initial
	CP=1;
always
	#5 CP=~CP;
initial
begin
	// start-up ： produce PE Rising edge , Preset 
	EN=1;PE=0;
	#10;
	EN=1;PE=1;
	#10;
	// Count 
	EN=1;PE=0;
	#260;
	// start-up ： produce PE Rising edge , Preset 
	EN=1;PE=1;
	#10;
	EN=1;PE=0;
	#20;
	// Pause 
	EN=0;PE=0;
	#20;
	$stop;
end

Simulation results

Show

Code implementation

Design module

//filename:_24show.v
module _24show(
input CP,EN,PE,BL,LT,
output [6:0] L1,L0);
/*  Input ：CP Clock signal ,EN Enable signal ,PE Prefabricated signal ,BL,LT, */
wire [3:0]Q1,Q0;
wire BL1;
_24s U(CP,EN,PE,Q1,Q0);
assign BL1=BL&(Q1!=4'b0000);
_74HC4511 U1(1'b0,BL1,LT,Q1,L1); 
_74HC4511 U0(1'b0,BL,LT,Q0,L0);
endmodule
module _74HC4511(
input LE,BL,LT,
input [3:0] D,
output reg [6:0] L);   
/*  Input / output port description .  Input port ： LE,BL,LT To enable the signal .D Four binary digits to be displayed .  Output port ：L by 7 Working condition of each segment of segment display . */
wire [2:0] E;   
assign E={
    LE,BL,LT}; // The intermediate variable is used for the subsequent priority judgment of the control end 
[email protected](*)
begin
    if(LE==0&&BL==1&&LT==1)
	begin
	  case(D)
	    //0-9 Show .
		4'b0000:L=7'b111_1110;
		4'b0001:L=7'b011_0000;
		4'b0010:L=7'b110_1101;
		4'b0011:L=7'b111_1001;
		4'b0100:L=7'b011_0011;
		4'b0101:L=7'b101_1011;
		4'b0110:L=7'b001_1111;
		4'b0111:L=7'b111_0000;
		4'b1000:L=7'b111_1111;
		4'b1001:L=7'b111_1011;  
		// The following is invalid 
  		4'b1010:L=7'b000_0000;
  		4'b1011:L=7'b000_0000; 
  		4'b1100:L=7'b000_0000;
  		4'b1101:L=7'b000_0000;
  		4'b1110:L=7'b000_0000;
  		4'b1111:L=7'b000_0000; 		
	   endcase
	end
    else 
	begin
	    casex(E)
		3'bxx0:L=7'b111_1111;  // Lamp test 
		3'bx01:L=7'b000_0000;  // Lights out 
		3'b111:L<=L;			// Latch 
		  endcase
	end
end
endmodule 

Test module

//filename:tb_show.v
`timescale 100ms/10ms
module tb_show();
reg CP,EN,PE,BL,LT;
wire [6:0] L1,L0;

_24show U3(CP,EN,PE,BL,LT,L1,L0);


initial 
	$monitor($time,"\tL1=%b,L0=%b\n,",L1,L0);
initial
	CP=1;
always
	#5 CP=~CP;
initial
begin
	BL=1'b1;LT=1'b1;EN=1;PE=0;
	#10;
	BL=1'b1;LT=1'b1;EN=1;PE=1;
	#10;
	BL=1'b1;LT=1'b1;EN=1;PE=0;
	#260;
	$stop;
end
endmodule

Simulation results