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To put it bluntly, it is realized MIPI Physical interface layer .MIPI D-PHY Implemented a D-PHY RX Interface , And provided with CSI-2 Compatible physical protocol layer support . When the link rate is greater than 1.5Gb/s when ,MIPI D-PHY Support jitter mode detection . You can see PG202 Learn more .

MIPI D-PHY Explain https://blog.csdn.net/weiaipan1314/article/details/125756016?spm=1001.2014.3001.5501

2.2 MIPI CSI-2 RX Controller

MIPI CSI-2 RX The controller consists of MIPI CSI-2 RX1.1 It consists of multiple levels defined in the specification , Such as channel management 、LLP layer 、 Byte to pixel conversion layer , To put it bluntly, it is realized MIPI Of CSI-2 agreement .

MIPI CSI-2 RX The controller core passes PPI from MIPI D-PHY The core receives 8 Bit data , Most support 4 Channels . As shown in the figure below ,PPI(Physical protocol interface) The byte data received on is then processed by the low-level protocol module , To extract real image information . Use of the final extracted image AXI4 Streaming protocols are provided to users / Processor interface . The channel management block is always starting from PPI Received 32 Run on bit data , It has nothing to do with the number of channels .

（1）1-4 Lane support , Registers support the selection of multiple channels ;

（2） Support all short packets and long packets ;

（3） Support primary and multiple secondary video formats ;

（4） data type (DT) staggered ;

（5） Virtual channel identifier (VC) staggered ;

（6） Data types and virtual channels are interleaved ;

（7） baotou 1bit Error correction code and 2bit Error detection ;

（8） Data load support CRC To verify ;

（9） For downstream IPs Long bag ECC/CRC Forwarding capability ;

（10） single lane Maximum support 2.5Gb/s The data rate of ;

（11） Pixel byte packaging based on data format ;

（12）AXI4-Lite Interface accesses core registers ;

（13） Low power state detection ;

（14） Error detection （D-PHY Level error 、 Packet level error 、 Protocol decoding level error ）;

（15） Provide interrupt support , Support internal status and error messages ;

As shown in the table below , Embedded non image （ The data type code is 0x12）AXI4 The data width of the stream interface is selected according to the selected data type . Embedded non image AXI4- The width of the stream interface increases with IP The width of the selected data type may be different .

2.3 ECC/CRC Forwarding

AXI4 Sideband signal of stream interface [ Include / It does not include video format bridges and embedded non image interfaces ] Will be from source [ sensor ] Received ECC and CRC Data is reported to downstream IP. This allows downstream IP Recalculate in some functional safety applications ECC/CRC.

In the wrong scenario , Such as sudden termination due to soft reset 、 Disable the core during packet transmission 、 The line buffer is full 、 The number of words in the received packet is greater than the actual payload , These sideband signals will not report correctly ECC and CRC.

2.4 VCX Support

MIPI CSI-2 standard v2.0 given VCX The support function is used to expand the maximum number of available virtual channels to 16 individual . When this feature is enabled , By combining 2 position VC Field （LSB） and 2 position VCX Field （MSB） To derive the virtual channel .

2.5 AXI Crossbar

Used in subsystems AXI Crossbar According to the address, the core will AXI4 Lite The request is routed to the corresponding sub core .

2.6 Video Format Bridge

The video format bridge core uses the user selected VC And data type information , Filter out only what you need AXI4 Stream data . The AXI4 Stream data is further processed based on data type information , The output is based on the number of pixels requested per shot .

The core processing of video format bridging is Vivado Integrated design environment (IDE) Data type selected in , And filter out from CSI-2 RX The received by the controller is based on RAW8 and Based on user definition data type (0x30-0x37) outside All other data types .

No matter Vivado IDE How about your choice ,RAW8 and Based on user definition The data type of is always handled by the video format Bridge Core . This allows multiple data types to support , Pixel data support comes from Vivado IDE A kind of The main data type , Metadata supports byte based data types defined by users . When transferring multiple data types ( for example ,RAW10 And based on user-defined data types ) when , The real pixel data is AXI4 Flow is defined .

For misaligned transfers , Not according to the TKEEP The signal specifies part of the final output for the output interface .

2.6.1 Width of video output port

video_out The width of the data port in the interface depends on the selected data type and the selected number of pixels per beat . Width is RAW8 and Vivado IDE The number of pixels per beat multiplied by the data type selected in Maximum . And then according to AXI4 The flow protocol rounds it to the nearest byte The border .

give an example 1： choice RAW10、 Each clock outputs 2 Pixel

Single pixel width of RAW10 = 10bit
Single pixel width of RAW8 = 8bit

For each clock, select two pixels ,RAW10 and RAW8 The effective pixel widths of are 20 and 16. The width of the video output port is configured as the maximum width of a single pixel , And round to the nearest byte boundary . This results in a video output port width of 24.

give an example 2： choice RAW7、 Each clock outputs 4 Pixel

Single pixel width of RAW7 = 7bit

Single pixel width of RAW8 = 8bit

For each clock, select two pixels ,RAW7 and RAW8 The effective pixel widths of are 28 and 32. The width of the video output port is configured as the maximum width of a single pixel , And round to the nearest byte boundary . This results in a video output port width of 32.

2.6.2 Pixels of various data types are packed

When transmitting multiple pixels with different pixel widths , Pixels with lower width Align to the most significant digit .

2.6.3 Embedded non image data type pixel packaging

AXI4 flow TDATA The width is based on from VivadoIDE Main data types selected in . This lists the embedded non image data type bytes in emb_nonimg_tdata Position on .

2.6.4 Pixel packaging when the video format bridge does not exist

The width of data port in video output can be from Vivado IDE Medium CSI-2 Options TDATA width Choose . When there is no video format bridge ,MIPI CSI-2 The receiving subsystem follows MIPI CSI-2 Standard recommended memory storage format output pixels , At this time, you need to check mipi CSI-2 Specification document for .

Examples of different data types are as follows ：

2.7 AXI IIC

MIPI CSI-2 Standard camera control interface （CCI） with 400 kHz Operation and 7 Bits from addressable I2C The quick mode variant of the interface is compatible . According to the user's choice ,AXI IIC Can be part of this subsystem .

3. MIPI CSI-2 RX application

Xilinx MIPI CSI-2 RX The controller realizes the camera serial interface between the camera sensor and the programmable device that performs baseband processing . Due to the development of high-resolution cameras , The camera - The bandwidth demand of sensor interface increases . Traditional parallel interfaces require more and more signal lines , This leads to higher power consumption . New high-speed serial interface , Such as MIPI CSI standard , These expanding bandwidth requirements can be met without sacrificing power consumption .MIPI It is a group of agreements defined by the mobile industry group , For standardizing mobile platforms （ Such as mobile phones and tablets ） All interfaces in . However , The huge capacity and economies of scale of the mobile industry force other applications to adopt these Standards . therefore , be based on MIPI Camera sensors are increasingly used in driver assistance technology in automotive applications 、 Video security surveillance camera 、 Video conferencing and emerging applications such as virtual reality and augmented reality .

4. performance

This section details the performance information of various core configurations .

4.1 CSI2 RX Subsystem delay

CSI2 RX The core delay of subsystem is from Transmission on the serial line begins （SoT） Behavior To CSI-2 RX Subsystem output tvalid Signal assertion Time for . This includes D-PHY Delay 、MIPI RX Controller delay and VFB Delay （ If the subsystem includes a video format bridge ）.

4.2 D-PHY Delay

MIPI D-PHY RX The core delay starts from the transmission on the serial line （SoT） Behavior to PPI Upper activehs Time of signal assertion .HS_SETTLE The cycle is D-PHY Delay calculation plays an important role . The following figure provides various configurations D-PHY Delay of rxbyteclk The number of clocks .

4.3 MIPI CSI-2 RX Controller Delay

MIPI CSI-2 RX The controller core delay is from PPI On the interface activehs Assertion To control Valid signal assertion on the controller output Time for . The following figure provides various configurations MIPI CSI-2 RX Controller Delay of rxbyteclk The number of clocks .

4.4 Video suitable bridge （VFB） Delay

VFB The core delay is from VFB Input stream interface “tvalid” To VFB Output stream interface “tvalid” Time for . The following figure provides various configurations VFB Delay of rxbyteclk The number of clocks .

4.5 CSI2 RX Total number of subsystem delay clocks

The delay time can be improved by increasing the number of link channels .

5. Interface

5.1 Clock and reset

dphy_clk_200M:D-PHY The clock of , It has to be for 200MHz;

video_aclk： Provide core clock for all cores of subsystem ,7 The maximum size of the series is 175MHz,UltraScale+ The maximum is 250MHz, At this time, the clock frequency should be greater than or equal to lite_aclk clock frequency .

5.2 When there is a video format bridge AXI4 Streaming video interface

5.3 When selecting embedded non image interface AXI4 Stream interface

and 5.2 Agreement , Just a clock emb_nonimg_ Interface for output .

5.4 When the video format bridge does not exist AXI4 Stream interface

and 5.2 Agreement .

5.5 Other interfaces

The signal	Input and output	describe
csirxss_csi_irq	Output	come from CSI-2 RX Controller Interrupt （ High active ）
csirxss_iic_irq	Output	come from AXI IIC The interrupt （ High active ）
mipi_dphy_if	Input	DPHY Interface
rxbyteclkhs	Output	PPI High speed receive byte clock
dlyctrl_rdy_out	Output	IDEALYCTRL Ready signal output , The delay value depends on vtc Change to adjust

6. Register space

adopt axi_lite Interface can access MIPI CSI-2 RX controller 、IIC controller 、MIPI D-PHY All internal core components .

When AXI IIC When the core does not exist ,MIPI D-PHY Offset moves up and away from 0x1_0000 Start . Software drivers can deal with this problem seamlessly .

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