Chapter003 FPGA learning PWM LED breathing lamp

Hardware principle

The above equipment is similar to FPGA The comparison table of pins is as follows ：

Design objectives

The design goal is to make the above LED To achieve the effect of breathing lamp
The core goal is to FPGA Implemented on PWM（ Pulse width modulation ）, It's different from changing PWM The duty cycle in the cycle changes the equivalent voltage , Final realization LED The breathing effect of the lamp .【 Unclear PWM And breathing lamp is what little partner can be in CSDN Take remedial classes 】

Code editing

In this experiment Verilog Language code can be implemented with only one module , Therefore, the experiment does not involve the concepts of modularity and instantiation , Edit only one code module and one constraint file .

Input content

• The system clock
• System reset （ Low level active ）

Output content

• 1 individual LED The lamp

Therefore, the module code can be obtained （PWM_LED.v） as follows ：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/07/11 20:31:57
// Design Name: 
// Module Name: PWM_LED
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module PWM_LED(
    input sys_clk,      // The system clock 
    input sys_rst_n,    // System reset 
    
    output led          //LED The lamp 
    );

reg [15:0] period_cnt;     // Cycle counter frequency ：1kHz   cycle ：1ms   Count value ：1ms/20ns=50000
reg [15:0] duty_cycle;     // Duty cycle 
reg        inc_dec_flag;   //0  Increasing    1  Decline   
    
/***************************************************
                     main code
****************************************************/    

// Output according to the relationship between duty cycle and counter value LED
assign led = (period_cnt >= duty_cycle) ? 1'b1 : 1'b0;

// Cycle counter 
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)
        period_cnt <= 16'd0;
    else if(period_cnt == 16'd50000)
        period_cnt <= 16'd0;
    else
        period_cnt <= period_cnt + 1'b1;
end

// Increase or decrease the duty cycle at the beat of the cycle counter 
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        duty_cycle <= 16'b0;
        inc_dec_flag <= 1'b0;
    end
    else begin
        if(period_cnt == 16'd50000)begin    // timing 1ms
            if(inc_dec_flag == 1'd0)begin   // Incremental mode 
                if(duty_cycle == 16'd50000)
                    inc_dec_flag <= 1'd1;
                else 
                    duty_cycle <= duty_cycle + 16'd25;
            end
            else begin
                if(duty_cycle == 16'd0)
                    inc_dec_flag <= 1'd0;
                else 
                    duty_cycle <= duty_cycle - 16'd25;
            end
        end
    end
end    
      
endmodule

Constraint code

#IO constraint 
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]
set_property PACKAGE_PIN U18 [get_ports sys_clk]
set_property PACKAGE_PIN N16 [get_ports sys_rst_n]
set_property PACKAGE_PIN J16 [get_ports led]

At this point, a binary stream is generated , And download （ I don't know how to download it. See you Chapter001）

experimental result

Second from top to bottom LED The lamp has a breathing effect , So the experiment was successful ！