[advanced semiconductor process technology series] FinFET process flow

1. Silicon substrate preparation ;
2. Deposit SiO2 and Si3N4 As a hard mask ;

3. Deposit polysilicon auxiliary layer ;
4. A hard mask auxiliary layer is formed by photolithography and etching ;

5. Deposit SiO2; Control by controlling the deposition time SiO2 The thickness of the , To control Fin Width Wfin
6. Etching SiO2 Form side wall ,Si3N4 As a stop layer ;

7. Remove the polysilicon auxiliary layer ;
8. utilize SiO2 As a hard mask , Etching forms an active region ;

9. Remove SiO2;
10. utilize HDP CVD Deposit SiO2, And pass CMP Flatten ,Si3N4 As a stop layer ;

11.SiO2 Recollection , The active area protrudes SiO2 The surface of the , Control by controlling the time of retracing Fin Height ;
12. Remove Si3N4;

13. Deposit SiO2 and Si3N4 As a barrier layer for hard mask plate and well ion implantation ;
14. Remove the bottom by lithography and etching Si3N4;

15. Get rid of SiO2;
16. Through two lithography and two large angle ions IMP formation NW and PW,Si3N4 As a barrier ;

17. Get rid of Si3N4;
18. utilize HDP CVD Deposit STI, And pass CMP Flatten ;

19.STI Recollection , The active area protrudes STI The surface of the , Control by controlling the time of retracing Fin Height ;
20. Lithography and channel ion implantation ;

21. Deposit SiO2 Buffer layer ;
22. Depositing polysilicon gate , stay ILD Then it will be removed SiO2 Buffer layer and polysilicon , Then deposit HfO2 And metal grating ;

23. The gate is formed by photolithography and etching ;
24. Deposit SiO2 and Si3N4 As a side wall ;

25. Etch to form grid side wall ;
26. Deposit SiO2 As an epitaxial growth barrier ;

27. Make... By photolithography and etching PMOS The source drain active region of is exposed ;
28. epitaxial growth PMOS Source drain active area SiGe Epitaxial layer ;

29. Remove SiO2 and Si3N4 Barrier layer ;
30. Deposit SiO2 and Si3N4 As NMOS SiC Epitaxial growth barrier ;

31. Make... By photolithography and etching NMOS The source drain active region of is exposed , Remove NMOS Source leakage SiO2 and Si3N4;
32. epitaxial growth NMOS Source drain active area SiC Epitaxial layer ;