Why is risc-v architecture gaining momentum

Related references ：

• RISC-V The official website of the development foundation

RISC-V Related progress

• MIPS Announce transformation and high-performance expansion RISC-V framework , Release the first batch of processors IP kernel

Basic concepts

Instruction set ： A set of instructions , Instructions are the smallest unit of the processor

Instruction set architecture ： The intermediate abstraction layer between the underlying hardware of the processor and the software running on it , Including data types 、 The storage model 、 Processor status visible to software 、 Instruction set 、 Instruction model and external interface

Microarchitecture ： The specific hardware implementation scheme of the processor

CISC： Complex instruction set architecture , Contains commonly used and infrequently used instructions of the processor , There are many instructions

RISC： Reduced instruction set architecture , For less commonly used operations , By executing the combination of several common instructions , The number of instructions is relatively small

32 Bit and 64 position ： The number of bits in the processor instruction set architecture , Generally refers to the width of general-purpose registers

Development track

History first ：RISC-V The architecture is mainly developed by the University of California, Berkeley Krste Asanovic professor 、Andrew Waterman and Yunsup Lee Wait for developers to 2010 The invention of , And got the leader of computer architecture David Patterson Strong support . Based on the problems of the previous architecture ,RISC-V Architecture was born .2016 year ,RISC-V The foundation was officially established and began to operate , It is a non-profit organization , Responsible for maintaining standards RISC-V Instruction set manual and architecture documentation , And push RISC-V The development of Architecture .

RISC-V Architecture goal ： Become a completely open instruction set , It can be freely used by any academic institution or business organization ; Become a standard instruction set that is really suitable for hardware implementation and stable .

RISC-V Instruction set architecture features ：

• A modular subset of instructions ：RISC-V The instruction set of is organized in a modular way , Each module is represented by an English letter （Volume 1, Unprivileged Spec v. 20191213 Directory visible ）
• Configurable general purpose register set ： Support 32 position /64 An architecture , Use separate integer general-purpose registers and floating-point register sets
• Regular instruction coding ： Regular coding , The index of the general register set required by the instruction is placed in a fixed position
• Simple memory access instructions ： And RISC The architecture is similar , Use only LOAD and STORE Instruction access memory ,
• Efficient branch jump instructions ： Use conditional jump instructions , No need to use the status register ; about CPU To determine whether to use different branch predictions , By default, static branch prediction technology is used
• Simple subroutine calls ： The information saved when the subroutine is called is placed in the Public Library
• Unconditional code execution ：RISC-V For any conditional judgment, use ordinary conditional branch jump instructions
• No branch delay slot ：MIPS This usage is often used in architecture , But it will make the hardware design complex
• Zero overhead hardware loop ： Use self increasing or self decreasing instead
• Simple operation instructions ： For operation exceptions , The hardware will only return a default value , Leave the rest to the software
• Compress a subset of instructions
• Privilege mode ： Machine mode 、 Supervision mode 、 User mode
• CSR register ： Control and status registers
• Interrupts and exceptions
• Vector instruction subset
• Custom instruction extensions ： Support for third party expansion

All in all ,RISC-V Generally, it revolves in one direction ： Reduce hardware pressure .

common RISC-V Commercial version and open source version ：Rocket Core、BOOM Core、Freedom SoC、LowRISC SoC、PULPino Core and SoC、PicoRV32 Core、SCR1 Core、ORCA Core、Andes Core、Microsemi Core……