Verilog for loop (1)

This introduction is currently in verilog In language , The only cycle that can be integrated into a circuit ： Constant number of cycles for loop .for The general form of a cycle is ：

for(variable = start_value;continue_condition; circle_express)
begin
       operations……
end

among ,varible It's a variable name ;start_value Is the initial value of the variable ;continue_condition Is the continuation condition of the cycle ;circle_express Is the step operation of each cycle ;operations Is the operation of each cycle . If you want to for Cycles can be integrated , The number of cycles must be a definite value .

Here's an example for The integrable characteristics of the cycle ：

for(loop=0; loop<10; loop=loop+1)// Integrable , The number of cycles is 10
for(loop=0; loop<10; loop=loop+2)// Integrable , The number of cycles is 5
for(loop=variable; loop<10;loop=loop+1)// The initial value is variable and cannot be synthesized 
for(loop=0; loop<variable;loop=loop+1)// The end condition is that the variable cannot be synthesized 
for(loop=0; loop<10; loop=loop+ variable)// Step size is variable and cannot be synthesized 

Here's how for Loop is the key code for the practical application of multi-level register chain ：

module DFF_link(
    input  clk,
    input  rst,
    input  [7:0] data_i,
    output [7:0] data_o
);
   localparam  Number_reg = 16;  // Define the number of registers that need to be cycled 
   reg[7:0] dff[Number_reg-1:0];// For this example 16 A register 
 
   integer loop;// Cyclic variables are best defined as integer
                   // When defined as reg Pay attention when designing loop A wide  
   [email protected](posedge clk or negedge rst)
      if(!rst)
         begin
            for(loop= 0; loop <= Number_reg-1; loop = loop+1)
                 dff[loop]<= 8'd0
         end
      else
         begin
            dff[0]<=data_i;
            for(loop= 1; loop <= Number_reg-1; loop = loop+1)
                dff[loop]<= dff[loop-1]
         end                    
  assigndata_o = dff[15];   
endmodule

We need to understand , There is no loop This variable , It only works in synthesis , Tell the synthesizer software to repeat several times for operation .

for Circulation in actual engineering , It has great practical value , It can greatly simplify the code , Improve work efficiency , We can think of it as c In language for The circulation function is the same , But in verilog Pay attention to its use rules and c Different language .